Packaging of integrated circuitsCopyright: © IWE 1
Our institute has a lab for standard processes for the packaging of integrated circuits. It includes Reflow ovens, thick and thin wire bonders, as well as flip-chip bonders.
Center for Micro and Nanotechnology (CMNT)Copyright: © IWE 1
Together with two other institutes, IWE 1 has been operating a modern clean room with a total area of 750 m2 since the end of 2003. Here we can perform all necessary processes for the fabrication of microsystems.
The IWE 1 is provided with oxidized wafers by the Institute for Power Electronics and Electrical Drives (ISEA). The lithography laboratory is used to realize microscopic structures. For this, an exposure machine from the company Süß is used.
Two sputter systems and a vacuum deposition system are used for metallization. Wafers can be cleaned by wet-chemical etching at modern wet benches. Electroplating stations allow the deposition os metallic layers.
The devices are processed and characterized from the bare silicon wafer to the complete structure.